High-Speed Interface Group

◈ High-speed interface 

    ◇ Introduction


- Recently, as the multimedia data increases, and the network of the wired and wireless internet is expanding, the needs
for high-speed data communication systems is greatly increasing. Digital data propagates through the channel which is
composed of printed circuit board (PCB) and package. As the data rate becomes several gigabits per second, the voltage
and timing margins at the receiver side are decreasing rapidly by channel loss, crosstalk, simultaneous switching noise
(SSN), and reflection. In order to accomplish such high data rate, the transmitter must assure high signal integrity and the
receiver must generate accurate synchronous timing within the constraint of power efficiency and systems cost.

- High-Speed Interface Group in IELAB strives for the researches about high-speed signaling systems by modeling of the
on- and off-chip interconnect and design of the signaling and clocking circuitry such as transmitter (TX), receiver (RX),
phase-locked loop (PLL), delay-locked loop (DLL), and clock- and data-recovery (CDR) circuit.


    ◇ Research area
      · On- and off-chip channel modeling
      · High-speed signaling systems for various application
          - Graphics DRAM interface
          - Mobile DRAM interface
          - Intra-panel interface for flat-panel display
          - Etc.

    ◇ Research results
      · Channel modeling for high-speed flat panel display driver IC
          - Modeling tool: Ansoft Q3D, Synopsys Raphael, HSPICE

High-Speed signaling system

    ◇ Research results
      · Clock- and data-recovery (CDR) with eye-tracking loop
          - Process: 0.18-mm CMOS
          - Area: 0.5 mm2
          - Data rate: 6.4-Gbit/s
          - RMS and pk-pk jitter of recovered clock: 12.1 ps and 86.4 ps
          - Power dissipation: 73.9mW

Architecture of Proposed CDR

Chip Microphotograph

Eye Diagram of Recovered Data at 0.8-Gbit/s

Jitter of Recovered Clock at 0.8 GHz

    ◇ Research results
      · Transmitter with low-power high-speed 8:1 multiplexer
          - Process: 0.18-mm CMOS
          - Area: 0.05mm2
          - Maximum data rate: 10.0-Gbit/s
          - Eye-opening: 75 mV X 58 ps
          - Power efficiency: 5.69mW/Gbit/s

Architecture of Transmitter

Chip Microphotograph

Measured Eye Diagram with 27-1 PRBS Pattern
at 10-Gbit/s

    ◇ Research results
      · LVDS interface for flat panel display
          - Process: 0.35-mm CMOS
          - Maximum data rate: 1.34-Gbit/s with 3m coaxial cable
          - RMS and pk-pk jitter of PLL: 12.3ps and 34.9ps
          - Power dissipation: 128mW at TX and 35.5mW at RX

LVDS transmitter

LVDS receiver

    ◇ Research results
      · Low-power LVDS receiver for flat panel display
          - Process: 0.18-mm CMOS
          - Maximum data rate: 1.6-Gbit/s
          - Power dissipation: 4mW

LVDS receiver