- Recently, as the multimedia data increases, and the network of the wired and wireless internet is expanding, the needs
for high-speed data communication systems is greatly increasing. Digital data propagates through the channel which is
composed of printed circuit board (PCB) and package. As the data rate becomes several gigabits per second, the voltage
and timing margins at the receiver side are decreasing rapidly by channel loss, crosstalk, simultaneous switching noise
(SSN), and reflection. In order to accomplish such high data rate, the transmitter must assure high signal integrity and the
receiver must generate accurate synchronous timing within the constraint of power efficiency and systems cost.

- High-Speed Interface Group in IELAB strives for the researches about high-speed signaling systems by modeling of the
on- and off-chip interconnect and design of the signaling and clocking circuitry such as transmitter (TX), receiver (RX),
phase-locked loop (PLL), delay-locked loop (DLL), and clock- and data-recovery (CDR) circuit.